$display ("my_data=0x%0h en=%0b", my_data, en) // Default value of logic type is X Logic en // Declare a 1-bit logic type variable Logic my_data // Declare a 4-bit logic type variable But, a signal with more than one driver needs to be declared a net-type such as wire so that SystemVerilog can resolve the final value. SystemVerilog introduces a new 4-state data type called logic that can be driven in both procedural blocks and continuous assign statements. Note that reg can only be driven in procedural blocks like always and initial while wire data types can only be driven in assign statements. Types that can have unknown (X) and high-impedance (Z) value in addition to zero (0) and one (1) are called 4-state types. In this session, we'll look at 4-state and 2-state variables and two new data types called logic and bit. In the previous article, an overview of the major data types were given.
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